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• date: 9 March 2026
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Master RTL Design: Build a RISC-V SoC from Scratch using Synthesizable SystemVerilog
What you'll learn
✓ Master SystemVerilog fundamentals including data types, operators, modules, interfaces, and advanced language features for digital design.
✓ Write synthesizable SystemVerilog code following industry best practices to create reliable hardware designs for FPGA and ASIC implementation.
✓ Design and verify digital circuits from simple combinational logic to complex sequential systems using simulation and testbenches.
✓ Build complete digital systems through 20 hands-on labs, progressing from basic adders to a full RISC-V System-on-Chip (SoC).
✓ Debug and verify designs using self-checking testbenches and simulation techniques to ensure correct hardware behavior.
✓ Apply SystemVerilog interfaces and modports to create clean, maintainable hierarchical designs with simplified module connections.
✓ Understand the differences between simulation-only constructs and synthesizable code to avoid common design pitfalls.
Requirements
● Basic knowledge of Digital Logic Design is required
● Understanding of binary numbers and Boolean algebra (working with 0s and 1s)
● Familiarity with basic logic gates (AND, OR, XOR, NOT)
● Knowledge of combinational circuits like multiplexers and decoders
● Understanding of sequential circuits including flip-flops and registers
● Basic concepts of finite state machines (FSM)
Description
Become a Digital Design Engineer by Building a 32-bit RISC-V Processor
Welcome to a comprehensive, lab-driven journey into the heart of modern Silicon Design.
In this course, you will master SystemVerilog, the industry's most powerful language for hardware description and verification. But you won't just learn syntax. You will apply every concept to a semester-long project: Designing, Simulating, and Synthesizing a RISC-V based System on Chip (SoC).
What sets this course apart?
• We start with the RISC-V architecture and move through the datapath, controller, and memory units.
• You will implement the Open Bus Interface (OBI) and integrate peripherals like UART.
• Learn how to write code that isn't just "simulatable," but is fully Synthesizable for FPGA and ASIC.
• Master complex structures like FIFO buffers, Finite State Machines (FSMs), and Word-Aligned Memory.
By the end of this course, you will have
• A fully functional RISC-V Datapath designed by you.
• Deep knowledge of SystemVerilog data types, packages, and interfaces.
• A professional project to showcase in your portfolio.
What you will learn
• Design and verify a RISC-V CPU using synthesizable SystemVerilog.
• Implement complex hardware structures like ALUs, Register Files, and FIFO Buffers.
• Master FSM (Finite State Machine) design for hardware controllers.
• Understand and implement the Open Bus Interface (OBI) for SoC communication.
• Convert architectural specifications into efficient, high-performance RTL code.
• Handle Clock Dividers, Synchronous logic, and Memory Alignment like a professional.
Who this course is for
■ University students taking digital design, computer architecture, or VLSI courses who need to learn industry-standard hardware description languages
■ Recent graduates preparing for careers in FPGA design or ASIC design
■ Professional engineers working in hardware design who want to deepen their SystemVerilog knowledge and learn best practices for synthesizable code
■ Verilog users looking to transition to SystemVerilog and understand its advanced features like interfaces, modports, and enhanced data types
■ Hardware engineers who want hands-on experience building complete systems, from basic circuits to a RISC-V System-on-Chip





   
   
   

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