• views: 196
• date: 14 April 2025
• posted by: AD-TEAM

Using Vivado 2024

What you'll learn
Architecture of 3rd Gen SDRAM memories
Building Initialization, Write, Read modules from scratch
Building Self refresh & Auto refresh modules
Mode Register usage & Understanding Write and Read transactions of SDRAM
Use Micron SDRAM model to test codes

Requirements
Fundamentals of Digital Electronics and Verilog

Description
This course offers a comprehensive journey into SDRAM controller design, starting with Day 1, where learners explore the fundamentals of DRAM cell operation, including how read and write operations work and why periodic refresh is mandatory, followed by an overview of the evolution of DRAM controller generations and the basics of first-generation controller design. Day 2 delves deeper into the architecture of second and third-generation DRAMs, introduces the internal block diagram of an SDRAM controller, and outlines the course design roadmap. On Day 3, participants learn the importance of SDRAM initialization, build flowcharts and FSMs, and implement the INIT module with complete testbench coding. Day 4 focuses on auto-refresh mechanisms, covering the design and verification of the refresh FSM and control logic. Day 5 explains how SDRAM enters low-power self-refresh mode, guiding learners through FSM design and testbench development for the self-refresh generator. Day 6 explores mode register programming, detailing the transactions and configuration of key parameters such as burst length and CAS latency. Day 7 covers write path design, highlighting DQM pin usage, write timing, FSM construction, and testbench verification. Day 8 addresses read path design by teaching SDRAM read timing and the development and testing of the read module. Day 9 introduces enhanced write control by addressing how to manage write operations during auto-refresh events and building a refresh-aware write controller. Finally, Day 10 brings all components together—INIT, AREF, SREF, WRITE, READ, and MODE—into a unified SDRAM controller design, preparing learners with the foundational knowledge required to transition confidently into DDR-based memory system design.

Who this course is for
Anyone wish to work with modern memories.




   
   
   

Forex Trading

Crypto Trading. 20 USD Bonus after KYC

We need your support!
Make a donation to help us stay online
        
Bitcoin (BTC)
bc1q08g9d22cxkawsjlf8etuek2pc9n2a3hs4cdrld
	
Bitcoin Cash (BCH)
qqvwexzhvgauxq2apgc4j0ewvcak6hh6lsnzmvtkem

Ethereum (ETH)
0xb55513D2c91A6e3c497621644ec99e206CDaf239

Litecoin (LTC)
ltc1qt6g2trfv9tjs4qj68sqc4uf0ukvc9jpnsyt59u

USDT (ERC20)
0xb55513D2c91A6e3c497621644ec99e206CDaf239

USDT (TRC20)
TYdPNrz7v1P9riWBWZ317oBgJueheGjATm

0 1 2 3 4 5

| Print version |

	Information
		Users of GUESTS are not allowed to comment this publication.