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• date: 7 November 2026
• posted by: voska89

Software Overview

Cadence Xcelium provides a simulation environment for verifying hardware designs throughout the semiconductor development process. Engineers can use it to execute testbenches, examine simulated design behavior, and debug functional problems before a design reaches the silicon manufacturing stage.
Its integration with hardware description languages and verification methodologies supports complex verification workflows. Multi-core simulation capabilities can also help accelerate demanding workloads, including design-for-test (DFT) simulations.

Key Features

• Digital Design Simulation: Simulate and verify complex digital logic, SoC, and IP designs.
  
• HDL Support: Work with SystemVerilog, Verilog, VHDL, and SystemC design descriptions.
  
• UVM-Based Verification: Support verification workflows using UVM-based testbenches.
  
• Design Debugging: Identify functional mismatches, logic errors, and other issues during hardware development.
  
• Multi-Core Simulation: Accelerate supported simulation workloads through multi-core processing.
  
• Spectre XScale Distributed Processing: Spectre AMS Designer supports XScale Distributed Processing (XDP) for distributing Spectre solver workloads across multiple machines and cores.
  
• Analog Solver Control: New SystemVerilog, Verilog, and Verilog-AMS system tasks allow testbenches to modify Spectre solver options and transient analysis parameters during simulation.
  
• Inverse Logic Support: Universal Connect Modules support logic-level swapping through the inverse_logic option.
  
• S-Parameter Analysis: Spectre S-parameter analysis can be performed on analog blocks during Spectre AMS Designer testbench time-domain simulations.

Why Choose Cadence XCELIUM Main

Cadence Xcelium provides a scalable simulation and verification environment for engineers working on advanced digital hardware. Its support for multiple HDLs and UVM-based testbenches makes it suitable for complex verification projects, while its debugging capabilities help identify design problems earlier in the development cycle.
The 25.09 release also extends analog and mixed-signal simulation workflows with distributed processing, additional solver controls, and S-parameter analysis support.

What's New in XCELIUM 25.09

• Spectre AMS Designer Support for XScale Distributed Processing (XDP): Distributed multi-machine simulation is supported for the Spectre solver. Workloads can be distributed across multiple machines and cores, improving scalability for complex testbenches containing numerous transistor-level subcircuits and parasitic elements.
  
• New System Tasks for Spectre Solver Options: The system tasks $cds_set_analog_param, $cds_get_analog_value$real, and $cds_get_analog_value$str allow Spectre solver options and transient analysis parameters to be controlled dynamically from SystemVerilog, Verilog, and Verilog-AMS testbench code.
  
• Logic-Level Swapping with inverse_logic: Universal Connect Modules support negative logic applications by swapping logic levels through the inverse_logic option, which can be enabled during IE card setup.
  
• S-Parameter Analysis in Virtuoso ADE: Spectre S-parameter analysis can be performed on analog blocks during Spectre AMS Designer testbench time-domain simulation, helping characterize high-frequency and linear networks through signal reflection and transmission measurements.

System Requirements

• Operating System: Linux
  
• Architecture: x86_64

Home Page

https://www.cadence.com/

Product Information

• Software Name: Cadence XCELIUM Main
  
• Version: 25.09 (006) HF006
  
• Architecture: x86_64
  
• Languages: English
  
• License type: Full Version
  
• File Size: 9.7 Gb

   
   
   

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