• views: 83
• date: 25 August 2024
• posted by: voska89

General Access Features delivered in Cerebrus 23.10.000
- Improved robustness of Re-baseline (using Scenario Replay in base flow) + Exploration (with or without -in_models)
- Ability to restart in a new path without moving the data
- Non-standard flow phases are made ignore_cost by default
- FPOPT support for designs without macro
- Command to compress scenario manually
- Default weight for dynamic/internal power set same as leakage
- Ctrl-C handling: Exit only when Cerebrus master is waiting
- Support for file based licensing and GUI (instead of http)
Early Access Features available in Cerebrus 23.10.000
- Automatically costing synthesis earlier than prects when ispatial not used
- New Fast mode option to adaptively handle PPA - TAT tradeoff
- Updates to CTS App to explore Clock tree parameters
Other recent updates (also back ported to Cerebrus 22.1x)
- CTS-postCTS, and Route-Postroute Flow Phases Combined for Costing
- Hold Cost enabled by default
- Combining Multiple Input Models into a Unified Output Model Feature
- Ignoring costing of non-standard flow phases automatically
- Exploring Margins Optimizer and PPA Primitives Concurrently
- Early Termination Based on Percentage of Base Scenario Metric Values
- WNS(100) Metric Made Default
Cadence Cerebrusis a transformational AI-driven technology that has a unique reinforcement learning engine, which automatically optimizes tool and chip design options to deliver better PPA with significantly less engineering effort and overall time to tapeout. As one example, the Cadence Cerebrus floorplan optimization feature enables customers to shrink the die size beyond a human's design potential. As a result, Cadence Cerebrus, when coupled with the broader Cadence digital product portfolio, provides a breakthrough engineering benefit with the industry's most advanced digital full flow, from synthesis through implementation and signoff. Cadence Cerebrus is part of the Cadence digital full flow, which includes the Innovus Implementation System, Genus Synthesis Solution and Tempus Timing Signoff Solution, and supports the Cadence Intelligent System Design strategy, enabling customers to achieve SoC design excellence.
Cadence Cerebrus Intelligent Chip Explorer Automated ML Chip Design Technology Overview
Venkat Thanvantri, VP of Machine Learning R&D, describes the innovative distributed computing and reinforcement learning technology that enables Cadence Cerebrus Intelligent Chip Explorer to deliver better PPA more quickly. Cerebrus, the Future of Intelligent Chip Design.
Cadenceis a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For eight years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work









   
   
   

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