SynThesis-STA-Physical Design(PD):Cadence+Synopsys Tool flow
Date: 2 December 2025 | Posted by: AD-TEAM
Synthesis-STA-Physical Design(PD):Cadence+Synopsys Tool flow
MP4 | Video: h264, 1920x1080 | Audio: AAC, 44.1 KHz
Language: English (US) | Size: 21.21 GB | Duration: 40h 50m
ASIC flow, Synthesis, STA, Physical Design - Cadence Genus, Tempus, Innovus tool flow & Synopsys ICC2 tool flow
What you'll learn
ASIC Flow in brief
Logical Synthesis vs Physical Synthesis
Timing Concepts, definitions
Static Timing Analysis (STA)
Timing paths, Contraints, modes
Synthesis example execution with Genus tool
STA example execution with Tempus tool
Physical design flow using Innovus tool
Floorplan
Placement
Clock Tree Synthesis (CTS)
Routing
Requirements
Basics of RTL design using Verilog
Digital Fundamentals
Verilog Language
Description
Section 1: Synthesis and Static Timing Analysis (STA) This course is intended for all levels of students, who want to gain knowledge in ASIC synthesis and STA. Electronics students, who want to internships, Engineers who want to start career in VLSI field. The course covers the following chapters: 1. ASIC flow in brief2. Logical synthesis Part 1 - inputs and outputs of synthesis, synthesis constraints, Libraries3. Logic Synthesis Part II - Synthesis demo using Cadence Genus tool flow4. Physical Synthesis - Various file formats and descriptions, Physical dimensions of gates5. Timing concepts - Setup time, hold time, slack. violations, timing budgets6. Static Timing Analysis - 7. Timing paths - Clock to output, propagation delay, input delay, output delay etc, STA using Cadence Tempus tool flow8. Timing constraints and various modes - MMMC9. Timing Exceptions - False path, multi cycle path10. Synthesis and STA assignment - APB TimerSection 2: Physical Design Flow using Cadence Tools - APB UART Design11. Inputs to Physical Design12. Innovus Tool Steps13. Floorplan14. Floorplan demo 15. Placement 16. CTS17. CTS Demo18. Routing19. SDC_MMMC_PVT Corners20. Physical Verification21. Physical design assignment using cadence innovus flow - APB Timer design Section 3: Physical Design Flow using Synopsys Tools - RISCV Processor Design22 DC Synthesis23. ICC2 Flow Introduction 24. ICC2 Initialization25. ICC2 Floorplan26. ICC2 PowerPlan27. ICC2 Placement28. ICC2 CTS29. ICC2 Routing & Chip Finishing30. Formality - Logic Equivalence Check (LEC)31. PrimeTime - Post Layout STA32. Synthesis and Physical Design Assignment using Synopsys tools - This course is intended for all levels of students, who want to gain knowledge in ASIC synthesis and STA. Electronics students, who want to internships, Engineers who want to start career in VLSI field. The course covers the following chapters: All the topics are elaborated with detailed examples, illustrated with diagrams, where required. Clear explanation; assignments added at the end of the course for practicing hands on examples. The lecture is given by hands on practitioners from the VLSI industry, who have worked on multiple projects and taped out chipsFor best take away from the course, kindly do hands on using tools (may be available in your institutions/companies). All the best - Happy learning
Who this course is for:
Internship - BE/BTech/MTech students and Engineers with ECE/EEE background, Beginners who wants to start VLSI career in ASIC backend activities
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